1. Field of the Invention
The present invention relates to a delta-sigma modulator, and more particularly, to a delta-sigma modulator and dithering method including a dithering capability for eliminating idle tones.
2. Statement of the Problem
A delta-sigma modulator comprises an electronic device or circuit that digitizes an analog input and comprises a widely used analog-to-digital converter (ADC). FIG. 1 shows a delta-sigma modulator according to the prior art. The prior art delta-sigma modulator includes an integrator at the analog input and the output of the integrator is fed into a bitstream processor. The bitstream processor receives the analog input and generates a corresponding (serial) digital output bitstream. The output of the bitstream processor comprises the digital output of the delta-sigma modulator.
A common and known drawback of a prior art delta-sigma modulator is that the output typically includes unwanted noise. The prior art delta-sigma modulator as a consequence includes a dithering signal that is fed back into the input in order to at least somewhat randomize the analog input signal. The dithering signal can have a low amplitude so that the dithering is only effective at low input signal amplitudes or idle times.
One drawback of a prior art delta-sigma modulator is that erroneous outputs can be generated when the input is idle, including idle tones that are generated when the analog input contains direct current (DC) values or signals. During such periodicity, the output of the prior art delta-sigma modulator produces idle tones comprising noise spikes in the output. These noise spikes can be erroneously interpreted as digital values.
Another drawback in the prior art is that the dithering is always performed and is not activated as needed.